a. Field of the Invention
The present invention pertains generally to tools used to analyze integrated circuits during design and specifically to combining multiple static timing analyses in a useful manner.
b. Description of the Background
Integrated circuits (ICs) are extremely complex and contain an enormous number of components or cells. As the size of these components decreases, even more components can be manufactured on a single IC. The complexity of the ICs makes debugging an IC difficult and very labor intensive. Further, the sheer number of components, sometimes in the millions, may make pinpointing a problem area an enormous task.
Static timing analysis is a common method for finding problem areas of an IC during the design phase. The circuitry is simulated to determine if it meets the desired functionality. Generally, the static timing analysis can be run for several corner cases, such as high and low temperature, high and low voltages, and various processing conditions. As a check of the performance of the design prior to fabrication, many or all of the corner cases may be run and the design adjusted until all the corner cases pass.
Because of the complexities of some ICs, the run time to perform a static timing analysis is very long, sometimes requiring hours or days of computation time. In many cases, only a limited number of corner cases may be analyzed rather than fully evaluating every possible corner case. This leaves open the possibility that in some circumstances, a design that passes on the limited number of corner cases may actually fail in service.
It would therefore be advantageous to provide a system and method for identifying problem areas within a design prior to releasing the design to fabrication. It would be further advantageous to provide a system and method for identifying marginal problems with circuit timing, determining potential problem areas, and performing additional analysis on those areas as required.